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Cyrix M II Processor
The M II™ processor is a high-performance
CPU offering advanced processing on Windows® 95 and other operating systems. The M
II™ processor features MMX™ instructions, enhanced memory management unit, a
64-KByte internal cache and other state-of-the-art architectural features to achieve
higher performance and offer better value than competitive processors.
Architectural Overview
The M II™ processor operates at higher frequencies than the previous 6x86MX™
processor. Based on the proven 6x86™ processor core, the M II™ CPU is
superscalar in that it contains two separate pipelines that allow multiple instructions to
be processed at the same time. It features a 64-KByte internal cache, a two-level TLB and
a 512-entry BTB. The M II™ processor also contains a scratchpad RAM feature, supports
performance monitoring, allows caching of both SMI code and SMI data, and features a
superpipelined architecture that increases the number of pipeline stages to reduce timing
constraints and increase frequency scalability. It delivers optimum 16-bit and 32-bit
performance while running Windows® 95, Windows NT, OS/2®, DOS, UNIX® and other
operating systems.
Architectural Features Comparison
| ARCHITECTURAL FEATURES |
M II™ CPU |
Pentium II CPU |
| MMX Instruction Set |
X |
X |
| Superscalar |
X |
X |
| Superpipelined |
X |
X |
| Register Renaming |
X |
X |
| Data Dependency Removal |
X |
X |
| Multi-Branch Prediction |
X |
X |
| Speculative Execution |
X |
X |
| Out-of-Order Completion |
X |
X |
| 80-Bit FPU |
X |
X |
| Primary Cache (Data + Instruction) |
64K (unified) |
16K + 16K |
Technical Specifications
| Clocking |
2x, 2.5x, 3x, 3.5x flexible core/bus clock
ratios |
| L1 Cache |
64-KByte; write-back; 4-way associative,
unified instruction and data; dual port address |
| Bus |
64-bit external data bus; 32-bit pipelined
address bus |
| Pin/Socket |
Socket 7 pinout compatible (P55C) |
| Compatibility |
Compatible with Windows® 95, Windows NT,
Windows, UNIX®, OS/2®, and many other operating systems; runs thousands of 16-bit and
32-bit applications as well as the latest MMX-enhanced software. |
| Floating Point Unit |
80-bit with 64-bit interface; parallel
execution; x87 instruction set; IEEE-754 compatible |
| Voltage |
2.9-volt core with 3.3-volt I/O |
| Power Management |
System Management Mode (SMM); hardware
suspend; FPU auto-idle |
| Available Bus/Clock Options |
66/233 |
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