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This is part II of an article about the IA-64 technology that Merced will use. If you have missed part one then must I advise you to read that part first so that you will undertand more about this article.
Part one can be found here: http://www.crus.com/hardware/articles/ia64-1.html
Okey now when done with those first words lets continue to the article.

Simple decision structures or code branches are a severe performance challenge to out-of-order RISC architectures. In the simple "if-then-else" decision code sequence shown in the figure below, traditional architectures view the code in four basic blocks. In order to continuously feed instructions into the processors instruction pipeline, a technique called branch prediction is commonly used, as the name suggests, to predict the correct path. With this technique, mispredicts commonly occur 5 to 10 percent of the time causing the entire pipeline to be purged and the correct path re-loaded. A misprediction rate of just 5 to 10 percent can slow processing speed as much as 30 to 40 percent.

To address this problem and improve performance, the IA-64 architecture uses a technique known as predication. In the example above, predication begins by assigning special flags called predicate registers to both branch paths-"p1" to the "then" path and quot;p2quot; to the quot;elsequot; path. At run time the compare statement stores either a true or false value in the 1-bit predicate registers. Both paths are then executed by the processor but only the results from the path with a true predicate flag are used. Branches, and the possibility of associated mispredicts are removed, the pipeline remains full, and performance is increased.

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