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Boost in Floating Point and MMX Instruction Performance
A key component of the Cayenne core is the ability to execute four floating point operations per cycle using dual MMX instruction units. This will deliver over 1 GFLOP peak performance, a first for desktop PCs. In addition, the dual floating point reciprocal and reciprocal-square-root instructions will execute five times faster on Cayenne than on the Pentium II processor. These instructions are used extensively in lighting calculations for 3D image processing.

The net result is that Cayenne will deliver in excess of 10 million meshed triangles per second to an external 3D rendering engine – more than five times faster than the Pentium II processor. Lastly, Cayenne will deliver single-cycle throughput on standard x86 floating point instructions.

Cayenne Core Summary
The Cayenne core will feature a dual-issue floating point and MMX instruction unit, 64KByte L1 cache, and an enhanced sixth-generation integer unit. Processors based on the core will initially be manufactured using a .25-micron, 5-layer metal process. This includes a C4 process for flip chip assembly. As a result, the core die size is expected to be about 65mm².

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